[DEVICE]
Family = M4A3;
PartType = M4A3-512/160;
Package = 208PQFP;
PartNumber = M4A3-512/160-10YC;
Speed = -10;
Operating_condition = COM;
EN_Segment = No;
Pin_MC_1to1 = No;
Voltage = 3.0;

[REVISION]
RCS = $Revision:;
Parent = m4a3.lci;
SDS_File = m4a3.sds;
Design = p2037x01.tt4;
DATE = 6/4/02;
TIME = 13:03:14;
Source_Format = ABEL_Schematic;
Type = TT2;
Pre_Fit_Time = 1;
Synthesis = Exemplar;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;

[GLOBAL CONSTRAINTS]
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Run_Time = 0;
Set_Reset_Dont_Care = No;
Clock_Optimize = No;
In_Reg_Optimize = Yes;
Balanced_Partitioning = No;
Usercode = 0;

[LOCATION ASSIGNMENTS]
layer = OFF;
VA1 = pin, 108, -, -, -;
VA2 = pin, 110, -, -, -;
VA3 = pin, 112, -, -, -;
VA4 = pin, 114, -, -, -;
VA5 = pin, 135, -, -, -;
VA6 = pin, 137, -, -, -;
VA7 = pin, 139, -, -, -;
VA8 = pin, 107, -, -, -;
VA9 = pin, 109, -, -, -;
VA10 = pin, 111, -, -, -;
VA11 = pin, 113, -, -, -;
VA12 = pin, 133, -, -, -;
VA13 = pin, 136, -, -, -;
VA14 = pin, 138, -, -, -;
VA15 = pin, 140, -, -, -;
VA16 = pin, 142, -, -, -;
VA17 = pin, 143, -, -, -;
VA18 = pin, 147, -, -, -;
VA19 = pin, 149, -, -, -;
VA20 = pin, 151, -, -, -;
VA21 = pin, 153, -, -, -;
VA22 = pin, 158, -, -, -;
VA23 = pin, 160, -, -, -;
VA24 = pin, 103, -, -, -;
VA25 = pin, 102, -, -, -;
VA26 = pin, 101, -, -, -;
VA27 = pin, 100, -, -, -;
VA28 = pin, 99, -, -, -;
VA29 = pin, 98, -, -, -;
VA30 = pin, 97, -, -, -;
VA31 = pin, 96, -, -, -;
DS0 = pin, 163, -, -, -;
DS1 = pin, 165, -, -, -;
AS = pin, 132, -, -, -;
LWORD = pin, 164, -, -, -;
IACK = pin, 146, -, -, -;
VAM0 = pin, 159, -, -, -;
VAM1 = pin, 152, -, -, -;
VAM3 = pin, 148, -, -, -;
VAM4 = pin, 141, -, -, -;
VAM5 = pin, 162, -, -, -;
WRITE = pin, 161, -, -, -;
VACK = pin, 169, -, -, -;
VDEN0 = pin, 171, -, -, -;
VDEN1 = pin, 170, -, -, -;
VDCK0 = pin, 189, -, -, -;
VDCK1 = pin, 172, -, -, -;
VDIR = pin, 188, -, -, -;
HRST = pin, 168, -, -, -;
BA19 = pin, 207, -, -, -;
BA20 = pin, 206, -, -, -;
BA21 = pin, 205, -, -, -;
BA22 = pin, 204, -, -, -;
BA23 = pin, 203, -, -, -;
BA24 = pin, 202, -, -, -;
BA25 = pin, 201, -, -, -;
BA26 = pin, 200, -, -, -;
BA27 = pin, 197, -, -, -;
BA28 = pin, 196, -, -, -;
BA29 = pin, 195, -, -, -;
BA30 = pin, 194, -, -, -;
BA31 = pin, 193, -, -, -;
LADDR = pin, 192, -, -, -;
TPC0 = pin, 191, -, -, -;
TPC1 = pin, 190, -, -, -;
MD0 = pin, 49, -, -, -;
MD1 = pin, 48, -, -, -;
RA0 = pin, 10, -, -, -;
RA1 = pin, 9, -, -, -;
RA2 = pin, 8, -, -, -;
RA3 = pin, 7, -, -, -;
RA4 = pin, 6, -, -, -;
RA5 = pin, 34, -, -, -;
RA6 = pin, 33, -, -, -;
RA7 = pin, 32, -, -, -;
RA8 = pin, 31, -, -, -;
RA9 = pin, 29, -, -, -;
RA10 = pin, 28, -, -, -;
RA11 = pin, 27, -, -, -;
RA12 = pin, 26, -, -, -;
RA13 = pin, 25, -, -, -;
RA14 = pin, 22, -, -, -;
RA15 = pin, 16, -, -, -;
RA16 = pin, 15, -, -, -;
RA17 = pin, 14, -, -, -;
RA18 = pin, 13, -, -, -;
RCE = pin, 5, -, -, -;
RWE = pin, 35, -, -, -;
ROE = pin, 17, -, -, -;
FCK = pin, 187, -, -, -;
CKOUT = pin, 73, -, -, -;
CK = pin, 74, -, -, -;
SCKOUT = pin, 84, -, -, -;
SCK = pin, 83, -, -, -;
TP1 = pin, 38, -, -, -;
TP2 = pin, 39, -, -, -;
TP3 = pin, 42, -, -, -;
TP4 = pin, 43, -, -, -;
TP5 = pin, 44, -, -, -;
TP6 = pin, 45, -, -, -;
TP7 = pin, 46, -, -, -;
TP8 = pin, 47, -, -, -;
TXE0 = pin, 78, -, -, -;
TXE1 = pin, 71, -, -, -;
TXE2 = pin, 72, -, -, -;
TXE3 = pin, 86, -, -, -;
TXE4 = pin, 85, -, -, -;
TXE5 = pin, 87, -, -, -;
TXE6 = pin, 88, -, -, -;
TXE7 = pin, 89, -, -, -;
TXE8 = pin, 90, -, -, -;
AD0 = pin, 61, -, -, -;
AD1 = pin, 60, -, -, -;
AD2 = pin, 59, -, -, -;
AD3 = pin, 58, -, -, -;
AD4 = pin, 57, -, -, -;
AD5 = pin, 56, -, -, -;
AD6 = pin, 55, -, -, -;
AD7 = pin, 54, -, -, -;
CLAMP = pin, 93, -, -, -;
CLEN = pin, 119, -, -, -;
TAG = pin, 70, -, -, -;
BUSY = pin, 125, -, -, -;
TXI = pin, 92, -, -, -;
TXO = pin, 77, -, -, -;
MA0 = pin, 91, -, -, -;
MA1 = pin, 80, -, -, -;
MA2 = pin, 79, -, -, -;
MA3 = pin, 124, -, -, -;
EDP = pin, 117, -, -, -;
IEDP = pin, 118, -, -, -;
RD0 = pin, 4, -, -, -;
RD1 = pin, 3, -, -, -;
RD2 = pin, 37, -, -, -;
RD3 = pin, 36, -, -, -;
RD4 = pin, 21, -, -, -;
RD5 = pin, 20, -, -, -;
RD6 = pin, 19, -, -, -;
RD7 = pin, 18, -, -, -;
VAM2 = pin, 150, -, -, -;
VD0 = pin, 184, -, -, -;
VD1 = pin, 183, -, -, -;
VD2 = pin, 182, -, -, -;
VD3 = pin, 181, -, -, -;
VD4 = pin, 176, -, -, -;
VD5 = pin, 175, -, -, -;
VD6 = pin, 174, -, -, -;
VD7 = pin, 173, -, -, -;
BY16 = pin, 64, -, -, -;
ADC8 = pin, 69, -, -, -;
ADC16 = pin, 65, -, -, -;
CVT8 = pin, 68, -, -, -;
CVT16 = pin, 66, -, -, -;
HB16 = pin, 67, -, -, -;
IOWR = pin, 130, -, -, -;
IORD = pin, 129, -, -, -;
K1 = pin, 120, -, -, -;
LNK = pin, 126, -, -, -;
ACT = pin, 131, -, -, -;

[GROUP ASSIGNMENTS]
layer = OFF;

[RESOURCE RESERVATIONS]
layer = OFF;

[SLEWRATE]
Default = Slow;

[PULLUP]
Default = Up;

[NETLIST/DELAY FORMAT]
Delay_File = SDF;
Netlist = VHDL;

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Prefit_Eqn = Yes;
Page_Break = Yes;

[POWER]

[SOURCE CONSTRAINT OPTION]

[TIMING ANALYZER]

[INPUT REGISTERS]

[Pin attributes list]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[OSM Bypass]

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[Explorer User Settings]

[opt global constraints list]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[verilog synplify constraints.Verilog Standard V2001.Alias]