"<pre>
MODULE A2060B

title 'A2060B'

" Copyright (C) 2005 Kevan Hashemi, Brandeis University

" This program is free software; you can redistribute it and/or modify
" it under the terms of the GNU General Public License as published by
" the Free Software Foundation; either version 2 of the License, or
" (at your option) any later version.

" This program is distributed in the hope that it will be useful,
" but WITHOUT ANY WARRANTY; without even the implied warranty of
" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
" GNU General Public License for more details.

" You should have received a copy of the GNU General Public License
" along with this program; if not, write to the Free Software
" Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA


declarations

"Pins"
A pin 12;"LVDS input"
B pin 64 istype 'com';"LVDS output"
!RESET pin 37;"RESET"			
CK pin 38;"40 MHz clock input"
WAKE pin 66 istype 'com';"WAKE"
LB pin 65 istype 'com';"Loop Back"
DC1..DC16 pin 41..44,47..50,53..56,58..61 
  istype 'reg,keep'; "device command"
"IO1..IO10 pin 3,4,5,6,8,9,10,11,14 istype 'com,keep';"
TP1..TP4 pin 69,70,71,72 istype 'com,keep';"Test Points"


"Nodes"				
SA node istype 'reg';"Syncronized A"
DA node istype 'com';"125ns delayed A"
DDA node istype 'com';"250ns delayed A"
D1..D9 node istype 'reg';"delay for DA,DDA"
RS0..RS1 node istype 'reg,keep';"Receiver State bits"
ER node istype 'reg,keep';"Entry Register"
Q1..Q16 node istype 'reg,keep,pos';"Shift Registers"

"Sets"
rs=[RS1..RS0];"Receiver State set"

equations

SA:=A;
SA.clk=CK;

[D1..D9]:= [SA,D1..D8];
[D1..D9].clk= CK;
[D1..D9].aclr=RESET;

DA = D4 & !D5;
DDA = D8 & !D9;

declarations
rest=0;
command_receive=1;
clock_storage_register=2;
address_receive=3;

equations 

rs.clk=CK;
rs.aclr=RESET;

state_diagram rs;
  state rest:
    if SA&DA then command_receive
    else
      if !SA&DA then address_receive 
      else rest;
 
  state command_receive:
    if SA&DDA then clock_storage_register 
    else command_receive;
	
  state address_receive:
    if SA&DDA then rest 
    else address_receive ;
	
  state clock_storage_register:goto rest;	
equations

[ER,Q1..Q16,DC1..DC16].clk=CK;
[ER,Q1..Q16,DC1..DC16].aclr=RESET;

when (rs==command_receive) & DA then 
  [ER,Q1..Q16]:=[SA,ER,Q1..Q15];
else
  [ER,Q1..Q16]:=[ER,Q1..Q16].fb;

when (rs==clock_storage_register) then 
  [DC1..DC16]:=[Q1..Q16];
else
  [DC1..DC16]:=[DC1..DC16].fb;

WAKE = DC8;
LB = DC7;
B = A;

TP1=1;
TP2=0;
TP3=1;
TP4=0;

end