The Programmable Logic Head (A2060) is a LWDAQ device built around an in-system programmable logic device (PLD) that provides ten general-purpose logic IO (input-output) lines and a through-hold breadboard area for specialized circuits. The breadboard area has access to +15V, +3.3V, 0V, and −15V power supplies. The ±15V power supplies are switched on and off by the PLD. In addition to the ten logic IO lines, the circuit provides four user-defince indicator LEDs (light-emitting diodes) and individual LEDs for the sixteen LWDAQ command bits. There are two additional LEDs to indicate that the local ±15V power supplies are turned on.

We designed the A2060 for quick adaptation to suit new one-time LWDAQ device implementations. The RS-232 Interface (A2060C) is an example of such an adaptation.
S2060_1: LVDS Transceiver, power supply switches, 3.3-V regulator.
S2060_2: Programmable logic chip, programming connector, logic IO.
S2060_3: Indicator LEDs.
A206001B: Printed circuit board files.
P2060A01: Core logic chip code in ABLE, implements command receiver.
ispMACH4000: Data sheet for the Lattice Semiconductor programmable logic chips, LC4064V-100T (64 gates, ≈$10), LC4128V-100T, and LC4256-100T (256 gates, ≈$50). The "-100T" suffix indicates the 100-pin TQFP (thin, quad flat-pack) package. You may use any of these chips in place of U1. By default, we use the LC4064 for U1.
Programming Instructions: How to program the logic chip on another of our circuits, the A2037. These instructions apply almost exactly to the A2060. You may also consult the Lattice Semiconductor website to purchase programming cables and download programming software, which is free.
The A2060's sleep state power consumption violates the LWDAQ specification, which limits the sleep-state current consumption of devices to 5 mA from each supply. The A2060's 40-MHz oscillator raises its +5V current consumption to roughly 40 mA. But consumption from the ±15V supplies is less than 1 mA.