|Status Register||Most Recent Byte||Device Job Register||Device Address Register|
|Device Type Register||Device Element Register||Loop Timer||Version Numbers|
|Delay Timer||Data Address||Enable Device Power||Enable Clamp|
|Command Register||Repeat Counter||Configuration Switch||Software Reset Register|
The LWDAQ Driver (A2071) is a Long-Wire Data Acquisition (LWDAQ) Driver. You will find an introduction to the LWDAQ in the LWDAQ User Manual. The A2071 provides eight LWDAQ driver sockets, each of which may be connected to a LWDAQ device or a LWDAQ multiplexer.
|A2071A||LWDAQ Cotroller with 6U VME Interface|
|A2071E||LWDAQ Driver with Ethernet Interface|
We assume you are familiar with the LWDAQ Specification. The LWDAQ Driver (A2071) is backward-compatible with the LWDAQ Driver (A2037) in every respect.
The A2071E obtains its power from an external adaptor with a 5.5-mm diameter power plug. The nominal input voltage is 24 VDC at 1 A, but the A2071E is will tolerate a wide range of voltages. See the Power Supplies section below for more details. The A2071A obtains its power from the VME backplane.
The A2071 provides eight LWDAQ driver sockets. Each socket provides ±15V and +5V power for LWDAQ devices or multiplexers. It can provide up to 500 mA at ±15V, and 1000 mA at +5V to all its driver sockets combined. It allows you to monitor the power supply voltages, and to measure the total current drawn from them. You can cut off power to the driver sockets by writing to a register on the A2071. Turning the LWDAQ power off for a second, and then on again, resets all devices and multiplexers, and restores them to the sleep state.
The analog signal returned from a device to the driver is a low-voltage differential signal with dynamic range ±0.5V. The A2071 can handle this signal in three ways. The first is to pass it through a 10-kHz low-pass filter and digitize it with a 16-bit ADC (Sixteen-Bit Analog to Digital Converter). The A2071's adc16 job performs this digitization, stores the result in the driver's RAM (random-access memory), and increments the driver's data address. The second way to handle the analog signal is to pass it through a 5-MHz low-pass filter and digitize it with an eight-bit ADC. The A2071's adc8 job digitizes the 5-MHz signal, stores it in RAM, and increments the data address. The third way to handle the analog signal is to clamp it when it sits at a zero-level and digitize it with the eight-bit ADC when the signal attains its measurement value. The A2071's read job, when applied to a TC255P device, uses its clamp to perform correlated double-sampling of the returned image pixels.
To store measurements, the A2071 provides 8 Mbytes of static RAM. You lose the RAM contents if you turn the A2071 power off, but not if you reset the board or turn off power to the driver sockets. The U1 chip on the A2071 is its programmable logic chip. We describe how to re-program this chip below.
The front-panel indicators have the following functions. The red one at the top is RESET. The green one just below is BUSY. It turns on when the A2071 is busy performing an LWDAQ job. The three green lamps below that are driven directly from the LWDAQ power supplies. The top one is connected to +15V, the middle one to +5V, and the bottom one to −15V. If one of these lamps glows dimly, its supply voltage has dropped. If it does not glow, the power is off. Below the green lamps are four yellow lamps and four red ones. These are test pin lamps, numbered one through eight from the top down.
A 0x before a numerical value indicates hexadecimal notation. A * before a logic signal name indicates negation. An asserted logic signal is one for which the signal in its name is true. Thus WAKE and *SLEEP are the same signal on a LWDAQ device, but WAKE is asserted when SLEEP is unasserted. A true logic signal is HI, and a false logic signal is LO. A nibble is four bits, a byte is eight bits, a two-byte is sixteen bits, and a four-byte is thirty-two bits. A bit or nibble marked X can take any value without affecting the statement in which it is mentioned. When we respond to address 0x1X, we mean we respond to all addresses 0x10 to 0x1F. An LWDAQ component is one that conforms to the LWDAQ Specification. The target device of an LWDAQ system is the unique device that will receive the next command word from the LWDAQ driver.
The LWDAQ Manual contains set-up information for LWDAQ systems, including LWDAQ Drivers like the A2071. You can also consult the LWDAQ Driver (A2037) Manual for operation instructions that apply equally well to the A2071A and A2071E, and do not assume that you are using the LWDAQ Software.
Logic chip U1 is a LC4512V-75T176 non-volatile complex programmable logic device made by Lattice Semiconductor. We upload firmware to this chip through connector P2 with the help of a programming cable from Lattice Semiconductor. Logic chip U32 exists only on the LWDAQ Controller with VME Interface (A2071A), see S2071_12A. We program U32 through P8, see S2071_1A. The firmware files are available in the A2071 Code Directory. The ABEL source code files have names P2071vxx.abl, where xx is the version of the firmware and v is "E" for the main logic chip U1 A2071A/E and "A" is for U32 that exists only on the A2071A. The JEDEC compiled firmware files have names P2071Evxx.jed.
The LWDAQ Controller with VME Interface (A2071A) uses U32 to provide an interface between the LWDAQ controller and a VME backplane. We read out A2071As with a TCPIP to VME Interface such as the A2064A/F. The TCPIP-VME interface as an IP address, and each A2071A in the VME crate has its own twenty-four bit base address, as set by its base address switch array, S3. In the LWDAQ Software we select socket s of the driver with base address a by entering a:s for daq_driver_socket, where a is an eight-digit hexadecimal number. The top two digits of a are always zero. For example, "00800000:4" selects socket four on the driver with base addresss 0x800000.
The LWDAQ Driver with Ethernet Interface (A2071E) uses an RCM6700 embedded microprocessor made by Digi International (formerly Rabbit Semiconductor) to provide its TCPIP interface. The RCM6700 obtains its ethernet connection through J2. Its programming connector is P4. You will find the source code of the program that runs in the RCM6700 in the A2037 Code Directory. It is the same program we compile for the A2037E, A2064A, A2064F, and A2101A. The program file has name C2037Exx.c, where xx is the version of the code. The A2071 requires version 14 or later. You will find the compiled code, particular to the A2071, in the A2071 Code Directory. We compile and upload the software with Dynamic C and a programming cable, both available from Digi International.
We communicate with the A2071's controller state machine by means of a sixty-four byte address space. The controller's status and control registers reside in this space, as well as its RAM portal byte, through which we can write to and read from its eight-megabyte memory, in the case of the A2071A, or two-megabyte memory, in the case of the A2071A. In the A2071E we use the driver's on-board TCPIP interface to read and write these registers. In the A2071E, we use the TCPIP-VME interface that shares the same VME crate as the driver. In both casdes, the TCPIP messaging protocol) is the same. The following table gives the byte-by-byte address map of the A2071 controller.
|Byte Offset (Hex)||Byte Offset (Decimal)||Contents||Read-Write|
|00||0||hardware identification number||R|
|02||2||most recent byte||R|
|03||3||device job register||RW|
|05||5||device address register||W|
|0B||11||data address clear||W|
|0D||13||device type register||W|
|0F||15||device element register||W|
|12||18||hardware version number||R|
|13||19||firmware version number||R|
|14..17||20..23||delay timer (bytes 3..0)||W|
|18..1B||24..27||data address (bytes 3..0)||W|
|1D||29||enable device power||W|
|1F||31||enable adc8 clamp, delay adc16 count-down||W|
|20..21||32..33||command register (bytes 1..0)||W|
|22..25||34..37||repeat counter (bytes 3..0)||W|
|2A..2D||42..45||reserved for driver base address (bytes 3..0)||W|
|2E||46||reserved for driver address modifier||W|
The driver uses big-endian byte ordering in its address space. The most significant byte of a multi-byte register is the first byte in memory. We will describe each register in more detail in the following sections. The Read-Write column in the table tells you if location's contents can be written, or read from, or both. Note that most of the locations to which you can write cannot be read back.
In the A2071E, the TCPIP interface uses six address lines, CA5..0, as shown in S2071E_1, to address the sixty-four controller registers. In the A2071A, the controller logic sees the same signals CA5..0, but these are derived from the lower bits of the VME address as shown in S2071A_1. The first byte of the A2071A address space resides at the A2071A's base address. The base address exists in 24-bit VME address space, but not in 32-bit or 16-bit VME address space. The A2071A responds only to 24-bit reads and writes of type "byte" or "word", where "word" is two bytes. We use S3 to set the A2071A base address.
The base address lies on a 65536-byte boundary defined by BA23..16. We set BA23..16 with S3 as shown above. Each base adress bit is set by its own switch to be either 1 or 0. The lower sixteen bits of the base address are always zero, which forces the driver address space onto a 64-KByte boundary. Sitch S3 is shown in S2071_12A. The A2071A responds to any address within its 65536-byte address block. It ignores VME address lines A6-A15 so that its 64-byte block appears repeated 1024 times. Although the A2071A base address is only 24 bits long, or six hexadecimal digits, in the LWDAQ Software, we must still specify a 32-bit base address when selecting A2071As within a VME crate. So the 24-bit address 0x700000 will be written "00700000", and socket 3 on this driver will be "00700000:3".
The identification byte for the A2071 is 71 decimal. It is the byte at address zero, and you can use it to look for A2071 boards on the 512-Kbyte boundaries of the VME address space. The second byte in the A2071 address space is a status register. Here are the bit functions, with bit zero being the least significant bit.
|7||Delay Timer Enabled (DTEN)|
|6||Transmitting Device Command (TDC)|
|5||Transmitting Device Address (TDA)|
|4||Repeat Counter Non-Zero (!RCZ)|
|3||Device Controller Busy (BUSY)|
|2||Sixteen-Bit ADC Converting (BY16)|
|1||Loop Timer Enable (LTEN)|
|0||Run Settling Delay (RSD)|
You can determine if the A2071 have finished an LWDAQ job by watching the busy bit. The busy bit is set when DJR is not equal to zero. The green busy lamp on the front panel turns on when the busy bit is set. You can also determine if it is busy by looking at the device job register, which is what our software tends to do.
The most recent byte location contains the byte most recently written to RAM, and you can read it back without disturbing currently-executing data acquisition jobs.
The device job register (DJR) tells the driver to execute a LWDAQ job. See here for a list of LWDAQ jobs supported by the A2071, and the Driver Jobs section of this manual for a description of each supported job and its implementation. When you write your code to communicate with a particular type of device, consult the device manual and it will tell you which jobs you should execute to exercise its DAQ functions.
The device address register (DAR) determines which of the eight driver sockets will transmit device commands. Only one driver socket transmits at a time. The top nibble of DAR determines which driver socket is active. The socket nearest the reset button is active when DAR is 0x1X. The socket farthest from the reset button is active when DAR is 0x8X.
When you write to DAR, the A2071 disables all driver sockets except the one selected and enables the selected driver socket. Even if you write the same value a second time, the A2071 waits eight microseconds to allow the driver sockets to stabilize. It then transmits the lower nibble of DAR as a device address through the active driver socket. Devices will ignore this four-microsecond transmission, but multiplexers will receive it and select one of their branch sockets accordingly. The A2071 waits another eight microseconds for the multiplexer's branch sockets to stabilize, and is then ready to begin responding to any pending data acquisition job. While the driver selects a new device, it will accept a new LWDAQ job, but it will report that it is busy executing the job. Therefore, your software does not need to be aware of the delay between writing to DAR and beginning an LWDAQ job, so long as it polls the status or device job registers to decide when the job is done.
In all, therefore, it takes twenty microseconds to select a new device, and the A2071 does not check to see if the new the device address is equal to the previous device address. Doing so would be possible, but would cause problems when you plug a multiplexer into the driver in the middle of continuous data acquisition. If you are watching signals on an oscilloscope, you might see an otherwise inexplicable twenty-microsecond delay between writing to the device job register and the commencement of a device command.
Before you execute a device-dependent job, you must write the target device type to the device type register (DTR).
The table above gives the device types recognised by the A2071, and the firmware versions that support each type. Device-independent jobs ignore DTR.
When there is more than one sensor or transmitter in a target device, you must write to the device element register (DER) before you execute a device-dependent job. The driver interprets DER depending upon the job you want executed and the target device type. If you want to flash a light source, it selects one of the light sources using the DER. If you want to read an image sensor, it selects one of the image sensors using the DER. Device-independent jobs ignore DER.
After executing a loop job, or any other job that requires the driver to measure the loop time, the loop timer contains an eight-bit number giving the propagation delay in 25-ns units to and from the target device. With a short cable (twenty centimeters), the loop timer will be equal to 0x00. If there is no cable connected to the driver socket, or if the multiplexer or device is not performing the loop-back correctly, then the loop timer will be set to its maximum value, which is 0xF0, or 240 decimal. The signal propagation time along CAT-5 is approximately 5 ns/m each way, or 10 ns/m round-trip. Therefore, the loop counter will increase by one for every 2.5-m increase in cable length.
You can read the A2071 hardware and firmware version numbers out of byte addresses 18 and 19 respectively. The firmware version number tells you which firmware file set was used to program the A2071. The hardware version is set by resistors R12 and R13. When we insert R12, we set bit zero of the hardware version to zero, and R13 does the same for bit one. Thus we can compose the numbers 0-3 in binary. When the two are left open, the hardware version number is 3. We describe the meaning of the hardware version number in the Modifications section.
You set the exposure time for timed jobs, such as flash and toggle, using the delay timer. The timer has four bytes. The upper A2071 ignores the top byte, but you can write a 32-bit number to the timer location. You cannot read back the value of the delay timer, but you can check if it is running by reading the status register. The delay timer counts down with an 8-MHz clock, so each decrement is 125 ns. Write to the delay timer before you execute a flash_job. With the three lower bytes of the four-byte exposure timer set to 0xFFFFFF, we get the longest exposure the timer can support, which is approximately two seconds.
Note that the delay timer is a four-byte location. If you define a four-byte variable in your software, and you are using an A2071A, your VME interface may try to write the location in a single 32-bit data cycle. The A2071A does not respond to 32-bit data writes. It supports only 8-bit and 16-bit data access.
The A2071 provides footprints for up to four 10-ns static RAM chips, each providing 2M x 8 bits of storage. The A2071E has all four of these memory chips loaded, for 8 MBytes of total on-board memory, and the A2071A has only one for 2 MBytes. The A2071 stores digitized measurements in the RAM location pointed to by the data address. After the A2071 stores a byte in RAM, it increments the data address. You set the data address by writing to the data address location on the A2071. The address counter increments itself whenever the A2037 stores a byte. When the address counter reaches 0x7FFFFF, it returns to zero.
If you want to clear the address counter to zero, you can also write a zero to the data address clear location. We provide the data address clear location for backward-compatibility with the LWDAQ Driver (A2037).
The enable device power bit is the least significant bit in the byte at location 29. In A2071As, this bit resets to 0 on power-up and after either a hardware or software reset. In A2071Es, the enable device power bit resets to 1. When set to 1, the A2071 delivers ±15V and +5V power to the LWDAQ devices. When you write a 0 to the enable device power location, the A2071 disconnects all three power supplies to all its LWDAQ devices and multiplexer. You can use the enable device power bit to force all LWDAQ devices into the sleep state. Write a 0 to the bit, wait five seconds, and write a 1.
The enable clamp bit is the least significant bit in the byte at location 31. It resets to 1 on power-up and after either a hardware or software reset. When set to 1, the eight-bit ADC uses its AC-coupled dynamically-clamped input, which is useful for correlated double-sampling of serial analog data. When set to 0, the eight-bit ADC uses a DC-coupled analog input.
Starting with firmware version 12, the enable clamp bit serves also to control the manner in which the delay timer dictates the sample period of repeated adc16 jobs. When set, the delay timer starts counting down only after the sixteen-bit ADC has finished converting. When cleared, the delay timer starts counting down immediatly the adc16 job begins. The sampling period of the adc16 job will be 375 ns + (125 ns * D), where D is the value you write to the delay timer. In firmware versions 11 and under, clearing the enable clamp bit does nothing to the adc16 job. The delay timer always starts after the adc16 conversion is done.
The Command Register occupies two bytes and represents bits DC1 to DC16 of a LWDAQ command word. The command job transmits these sixteen bits to the target device. The DC16 bit is the most significant bit in the byte at location 32, and DC9 is the most significant bit in the byte at location 33. We arrange the bits in this manner because the A2071 assumes big-endian byte ordering for multi-byte numbers. Thus a two-byte integer will be stored with the most significant byte in the first location, and the least significant byte in the second location. If you have the LWDAQ command word in memory as a 16-bit integer, you can write this integer to location 32 with big-endian byte ordering, and the bits will be in the right place for transmission by the command job.
The controller will execute any job for us multiple times in a row if we write our desired number of executions minus one to the repeat counter. Each time the A2071 finishes a job, it checks the repeat counter. If the repeat counter is zero, the A2071 clears the device job register and enters its rest state. If the repeat counter is not zero, the A2071 decrements the counter and begins executing the same job again. If the job uses the delay timer, the A2071 restores the delay timer to the value it contained at the beginning of the first execution off the job. The A2071 saves a copy of the delay timer whenever we write to the delay timer, and restores the delay timer from this copy when it needs to. After the final repetition of the job, however, the A2071 leaves the delay timer at zero, and clears the delay timer copy as well.
When the repeat counter is one (1), and we write to the device job register, the A2071 executes the specified job twice. The total number of executions is equal to the value of the repeat counter at the beginning of the multiple-execution, plus one. The repeat counter is three bytes long, so its maximum value is 16,777,215 (0xFFFFFF).
When we read from the Configuration Switch location, we get a zero when the configuration swith is depressed, and a one when it is not depressed. The configuration switch exists only on the A2071E. The A2071E relay reads the configuration switch location when it starts up, to see if it should re-write its EEPROM with default configuration values.
You can reset the A2071 programmable logic chip, and the A2071E's ethernet interface, and the A2071A's VME interface, by writing a 1 to the software reset register. The chip will respond as if the hardware reset button on the front of the board had been pressed.
When we read a byte from the RAM Portal, we receive the byte in the controller memory at the location pointed to by the Data Address. After we read from the RAM Portal, the controller increments the data address, so that the next read from the RAM Portal will yield the next byte in the controller RAM. The same process works in reverse also, with consecutive bytes in the controller memory being written to through the RAM Portal. The RAM portal exists in all versions of the A2071E firmware, and versions nine and up of the A2037A firmware.
The following table lists the LWDAQ jobs supported by the A2071.
|wake||1||no||wakes up the device|
|move||2||yes||moves data within the device|
|read||3||yes||transfers data to driver|
|fast_toggle||4||no||toggles signal to device|
|flash||6||yes||flashes a transmitter|
|sleep||7||no||sends the device to sleep|
|toggle||8||yes||toggles a logic signal in the device|
|loop||9||no||measures cable loop time|
|command||10||no||sends specified command to device|
|adc16||11||no||16-bit 100 kSPS with storage|
|adc8||12||no||digitizes to eight bits and stores|
|delay||13||no||waits for a specified time|
|fast_adc||15||no||8-bit 40 MSPS with storage|
|reserved||16-63||reserved for future use|
After you write to DJR, the A2071 begins executing the job and sets the BUSY bit in the status register (bit 3). Your software can determine that the A2071 has finished executing the job either by reading the status register or by reading DJR itself, which will return the job number until the job is done. The busy light on the front of the A2071 lights up when BUSY is set. If you want to stop the A2071 in the middle of a job execution, you can do so by pressing the reset button on the front of the board, or you can write a zero to the DJR and the A2071 will abort the job immediately.
We now describe each of the jobs offered by the A2071. In the case of each device-dependent job, we list the device types for which the A2071 supports the job, and the required firmware version. We refer to the bits in a command word with the notation DC1..DC16.
The null job (0) does nothing. Writing null_job to DJR forces the A2071 to abort any other job execution.
The wake job (1) transmits a device command word containing a one (1) in the WAKE bit (DC8) and zeros in all other bits. The target device should wake up. An obsolete name for wake_job is "expose_job".
The move job (2) is device-dependent, and the A2071 supports it for TC255P devices, for which the job clears the image area of accumulated charge. Another name for the move_job is "clear_job".
The read job (3) is device-dependent. The A2071 supports the read job for several image sensors, for which the job transfers an image from the sensor into the driver memory, starting at the driver memory address given by the value of the data address register at the beginning of the job. At the end of the job, the data address will point to the byte after the last pixel of the image. In the case of a TC255 device, the image will be arranged as 244 rows and 344 columns. The image the A2071 reads out depends upon the value of the device element register (DER). If DER is one (1), the A2071 reads out CCD number one (1). If DER is any other number, the A2071 reads out CCD number two (2).
When applied to data devices, the read job performs byte transfer from a device by transmitting stop bits, as described in the Receive Signals section of the LWDAQ Specification. The read job, when applied to a data device, sends a single 125-ns LO pulse to the target device and then awaits a low pulse back from the target device of duration 50-ns followed by eight bits of a byte, with the most significant bit first, and each bit taking up 50 ns. These eight bits show up in the serial shift register register, and are stored as a single byte in the driver RAM. For details of the way the driver receives the serial byte, see here.
By means of the repeat counter, you can upload multiple bytes from a target device. You can check the most recent byte received from the data device by polling the most recent byte location. You can either upload a fixed number of bytes from the target device, or you can wait for a particular terminator byte to arrive, and then interrupt the read job by writing a zero to the job register. The uploaded bytes will be in RAM, ready to transfer off the driver.
When the relay reads from the most recent byte register, the controller waits until the read cycle is over before it stores the next uploaded byte in the most recent byte register. The controller must wait, or else it will corrupt the most recent byte value read out by the relay. The relay's read cycle takes of order 1 μs, so each time you read the most recent byte, you introduce a 1-μs pause in the upload of data from a data device.
The one-byte upload from a data device proceeds as follows. First, we write the number three to the device type register and the job register. Within 125 ns of receiving the job number, the controller sends out the falling edge of LO low pulse. The LO pulse lasts for 125 ns and is followed by a rising edge and over 375 ns of HI, thus making a stop bit. Immediately after the rising edge, the controller is ready to receive a serial byte from the data device. It waits until it receives a LO value back from the data device. Once it receives the LO, it waits 75 ns and samples the returned logic value. This value is the most significant bit of the incoming byte, or bit seven. It samples every 50 ns after that, until it has received eight bits. The final bit is bit zero. Once it has the eight bits, the driver waits until the relay is not reading or writing from the controller registers. Occasionally, the relay may be reading the most significant byte register. The controller clocks the eight bits into the most recent byte register, stores the eight bits in RAM, and increments the address counter. These final steps take 125 ns.
The maximum rate at which the driver can upload bytes from a data device occurs during a multiple read job (one for which the repeat counter is non-zero, so the job gets repeated automatically by the controller) during which the relay does not read from the most recent byte, and in which the data device begins transmission of its bits immediately after the rising edge of the driver's LO. Under these circumstances, the driver spends 125 ns in its rest state, 500 ns waiting for the byte, and another 125 ns storing the bytes. The total time for the byte transfer would be 750 ns. Any delay between the rising edge of the driver's low pulse and the data device's response will add to the read time. Such a delay is likely, because the target device must identify the driver's rising edge as part of a stop bit rather than a one or zero bit. This identification will take at least 357 ns. Byte transfer between the A2071 and the A2100 takes place at 1.1 MBytes/s. Each transfer takes 892 ns.
The fast toggle job (4) is identical to delay_job except that the logic signal transmitted to the target device is driven low when the repeat counter has an odd value. When used in conjunction with the delay timer and the repeat counter, the fast_toggle_job transmits a square wave to the target device. The period of this square wave is twice the execution time of a single fast_toggle_job. The execution time of a single fast_toggle_job is 375 ns plus the delay timer value multiplied by 125 ns. Thus the period will be (750 + 250d) ns, where d is the value of the delay timer at the start of the job execution.
The square wave transmitted to the device is not exactly symmetric. The transmitted signal is LO for (125d + 125) ns, but it is HI for (500 + 125d) ns. This assymmetry was not intentional, but the result of an oversight in the design of the firmware.
The alt move job (5) is device-dependent. The A2037 supports it for TC255 and TC237 devices, for which the job transfers an image from the sensor's image area into its storage area. Another name for alt_move_job is "transfer_job".
The flash job (6) is device-dependent. The A2071 supports it for several device types. In all cases, the job flashes a light source on the device for the length of time specified by the delay timer at the start of the job. The flash time is the delay timer value multiplied by 125 ns. In TC255 devices, the device element register specifies which of four sources to flash. In LED devices, the same register specifies which of six sources to flash.
The sleep job (7) transmits a device command word containing all zeros. The target device should go to sleep. The sleep_job takes 4 μs.
The toggle job (8) is device-dependent. The A2071 supports it for TC255 devices, for which the job toggles the TC255 anti-blooming gate input at 125 kHz for a length of time specified by the delay timer at the start of the job. Another name for toggle_job is "ab_expose_job". For more on anti-blooming, see the Anti-Blooming section of the Camera Head (A2056) Manual.
The loop job (9) transmits a device command word containing all zeros except in the WAKE (DC8) and LB (DC7), waits while the returned logic line settles, then transmits a logic low to the target device, and times how long it takes, in 25-ns increments, for the logic low to return to the driver. The A2071 stores this time, which we call the "loop time" in the loop timer location, from you can read it out. The loop_job takes up to 12μs depending upon the length of cable running to the target device.
The command job (10) transmits the sixteen-bit command specified by the command register. The least significant bit of the command register will be DC1, and the most significant will be DC16 . The command_job takes 4 μs.
The adc16 job (11) initiates and waits for a sixteen-bit ADC conversion by the A2071's ADS8505, and stores the result in the A2071 memory at the location pointed to by the data address at the beginning of the job. At the end of the job, the data address will point to the byte after the second byte of the sixteen-bit ADC output. Note that the A2071 arranges sixteen-bit words in big-endian order, so the most significant byte is the byte at the lower address.
The A2071 pauses for a time determined by the delay timer before it completes the adc16_job. The clamp enable bit (CLEN) alters the manner in which the delay timer dictates the sample period of repeated adc16 jobs. When CLEN is 1, the delay timer starts to count down after the sixteen-bit conversion. This conversion takes roughly 10 μs. The total time taken by the adc16_job is 10 μs + (125 ns * D), where D is the value you write to the delay timer.
Example: We wish to digitize an incoming analog signal at 100 Hz, for 100 s. We write 10,000 to the repeat counter, 80,000 to the delay timer, and 64 to the data address. Then we write 11 to DJR, and the A2071 executes the adc_16 job 10,000 times, each time waiting 10 ms after the conversion is complete before beginning the next execution. We note that the sampling period will be too long by the sixteen-bit conversion time of 10±1 μs, or 0.1%. We might subtract 80 from the value we write to the delay timer to account for this 10 μs. We would still be left with an uncertainty of 0.01% in the sampling rate. The A2071 oscillator is accurate to 50 ppm, or 0.005%.
With firmware version 12+ and CLEN set to 0, the delay timer begins to count down as soon as the adc16 job begins. The sampling period for repeated adc16 jobs will be 375 ns + (125 ns * D), where D is the delay timer value. This formula works so long as the sampling period is greater than 10 μs. Otherwise, the adc16 job waits for its conversion to complete, so the minimum sampling period remains 10 μs. Provided that the sampling period is greater than 10 μs, however, this new method of setting the sampling period allows us to set the period exactly, which is necessary for sinusoid amplitude measurements such as those performed by the Inclinometer Instrument.
Example: We wish to digitize the sinusoid from an Inclinometer Head (A2065), whose period is 854.49 μs. We want to capture a whole number of periods. We set the delay timer to 132 and the repeat counter to 557. The result is samples with period 16.875 μs spanning 9399.375 μs. Eleven cycles of the sinusoid occupy 9399.39 μs, so we are pretty close.
This adc8 job (12) causes an eight-bit ADC conversion and stores the result in the A2071 memory at the location pointed to by the data address at the beginning of the job. At the end of the job, the data address will point to the byte after the result. The adc8_job takes 500 ns plus the time specified by the delay timer at the beginning of the job execution. As with the adc16_job, we can repeat the adc8_job using the repeat counter, and set the sampling rate using the delay timer.
Example: We wish to digitize an incoming analog signal at 1 MHz for a period of 1 ms. We write 999 to the repeat counter, 4 to the delay timer, and 64 to the data address. Then we write 12 to DJR, and the A2071 executes the adc8_job 1,000 times, each time waiting 500 ns after it stores an eight-bit sample, so that the sample rate is exactly 1 MHz.
The eight-bit ADC on the A2071E is the ADS282, which is a 10-bit converter, but we throw away the least significant two bits to obtain our eight-bit result. It contains a pipeline for conversion results. The pipeline is five conversions long. The first adc8 job you execute will convert the incoming signal at the time of the adc8 job. But the data that the adc8 job stores in memory is the the data at the end of the pipeline. Thus adc8 job number n creates an eight-bit data value corresponding to sample instant n, but the eight-bit value that gets stored in memory corresponds to sample instant n−5.
The eight-bit ADC will run at up to 40 MSPS when we use it with the fast adc job, and with the adc8 job it will run at a top speed of 2 MSPS. The internal pipeline of the ADC puts a minimum value on the sample rate also. The minimum sample frequency is 10 kHz, which corresponds to a sample period of 100 μs. For slower sample rates, we can use the sixteen-bit ADC.
The delay job (13) simply keeps the A2071 busy until the delay timer counts down to zero. The BUSY bit will be set for 125 ns multiplied by the value of the delay timer at the beginning of the job, plus a constant 375 ns.
The fast adc job (15) performs continuous digitization and storage at 40 MSPS using the A2071's eight-bit ADC. The A2071 continues storing the samples until the delay timer counts down to zero, and stores them in consecutive memory locations, starting at the value pointed to by the data address at the beginning of the job execution. The number of samples stored in memory is approximately equal to the delay timer value at the beginning of the job execution, multiplied by five (there are five 25-ns sampling periods in each 125-ns delay timer clock period).
As with the adc8 job, the samples recorded by the fast adc job are delayed by four places compared to the sample commands. The first four samples recorded in memory will be indeterminate values. The fifth sample recorded will be the one corresponding to the first conversion of the fast adc job.
At the time of writing, the fast adc job is not used by any of the standard LWDAQ Instruments. To test the fast adc job, we use a Toolmaker script that you will find here.
The A2071 uses the ADS8805 sixteen-bit ADC (analog to digital converter). The adc_16 job digitizes the LWDAQ return voltage and stores the two-byte result in memory. The ADC produces a sixteen-bit output representing its ±10-V input range as a two's compliment signed binary value. The gain from the LWDAQ return voltage to the ADC input is 16. The LWDAQ return voltage is the difference between the LWDAQ R+ and R− lines. The dynamic range of the ADC in terms of return voltage is ±0.625 V, which includes the nominal ±0.5 V dynamic range of R defined in the LWDAQ Specification.
|Return (V)||Input (V)||Result (hex)||Result (decimal)|
You can measure the input noise of the ADC and its amplifiers by selecting device address eight (8 or 0x08). This address selects a reference zero-value for the return voltage using the power monitor circuit. The stochastic noise on this input, as seen by the sixteen-bit ADC, is less than five counts. At the LWDAQ return signal, the noise amounts to less than 100 μV.
The sample_A2037E_adc16 routine in electronics.pas illustrates the use of the sixteen-bit ADC data. The LWDAQ_daq_Diagnostic routine in Diagnostic.tcl shows how the Diagnostic Instrument acquires sixteen-bit ADC samples from an A2071E directly, or from an A2071A through a TCPIP-VME Interface such as the A2064.
The input of the sixteen-bit ADC is preceeded by a four-pole 10-kHz low-pass filter with a Butterworth response. The filter takes less than a millisecond to settle after a step change, but more than a hundred microseconds. We recommend you allow the filter to settle for a millisecond before you start recording its input. You can obtain the millisecond delay by setting the driver's delay timer and executing a delay job. If you would like to increase the resolution of your measurement, you can take the average of many consecutive samples, which is what the Diagnostic Instrument does when it measures the LWDAQ power supplies.
The 10-kHz low-pass filter (U20 and surrounding parts in the schematic) is made of two active filter stages, each of which implements two poles of the filter transfer function. The garph above shows its measured frequency response. If you are interested in the theory behind this filter, take a look at our Filter Design Guide.
The A2071 uses the ADS828 10-bit 75-MSPS ADC from Texas Instruments. The adc8 job digitizes the LWDAQ return voltage and stores the most significant eight bits as a single-byte in RAM. The least significant two bits produced by the ten-bit converter we discard. The input to this ADC passes through either a 5-MHz low-pass filter, or through a black-level clamping circuit. By default, the A2071 selects the clamping circuit, which it uses for image readout. You can disable the clamp by writing a zero to the clamp enable location. When the clamp is applied, the ADC digitizes the change in return voltage from its value when the clamp was applied. The measured frequency response of one 5-MHz low-pass filter is plotted here.
The LWDAQ return voltage, R, is the difference between R+ and R−. The ADC accepts inputs from 1.0 V to 2.0 V. An input of 1.0 V yields a result of 0 (0x00) and an input of 2.0 V yields a result of 255 (0xFF). The analog gain from R to the input is 1.0, with a conversion from differential to single-ended. With the clamp turned off, −0.5 V on R becomes 1.0 V at the ADC, for a result of 0x00, while +0.5 V becomes 2.0 V, for a result of 0xFF. Thus the dynamic range of the eight-bit ADC in terms of R is ±0.5V with the clamp turned off. When we use the clamp, the clamp voltage appears as 1.1 V at the ADC input, for a result of 24 (0x18). A voltage 0.9 V higher than the clamp appears as 2.0 V for a result of 255 (0xFF). We shift the clamp voltage to 1.1 V instead of 1.0 V so that we will be sure to see noise above and below the clamp voltage in our images. Thus the black level in our images is not going to be zero, it will be around 24 counts.
The clamp works only when it is pulsed every time we digitize R, and only when the clamping is synchronous with a periodic signal. The image readout jobs, like read_job applied to a TC255 device, perform the synchronous clamping for us, provided that the clamep enable bit is set. But if we want to use the eight-bit ADC for some other purpose, we must clear the clamp enable bit first. Then we execute the adc8 job and read out the result from RAM. The eight-bit ADC is used by both the adc8 job and the fast adc8 job.
The A2071E obtains its power from a single DC power supply, such as the 24-V, 1.7-A GS40A24-P1J. The power plug must have outer diameter 5.5 mm and inner diameter 2.1 mm. The A2071E contains a bridge rectifier that allows it to use either center-positive or center-negative connectors. The A2071A obtains its power from the VME backplane. Both circuits apply their 24-V input to drive three DC-DC converters that produce +3.3V, +5V, +15V, and −15V power supplies.
The A2071E draws 220 mA quiescent current from 24 V with no devices plugged in, or 310 mA from 18 V. It draws 300 mA when capturing images from a single camera. When we draw 500 mA from ±15 V and 1 A from +5V, the 24-V current consumption reaches 1 A. Thus we obtain full-power operation of the A2071E with a 24-V, 1-A power supply. The A2071E will operate for power supply voltages anywhere between 18-V and 36-V. So long as the power supply delivers 25 W or more, the A2071E will deliver full power to the devices.
The A2071 power supplies are generated by its on-board DC-DC converters. The ±15 V supply is provided L2 in the schematic, which is JCK1524D15, AEE00CC18-LS or equivalent. These converters have a rated output current of 500 mA. The +5 V supply is provided by L3 in the schematic, which is JCH1024S05, or equivalent. These converters are rated at 2,000 mA. There is another converter on the A2071E circuit to create 3.3 V for the embedded microprocessor and controller logic. This converter is L1 in the schematic, and is PYB10-Q24-S3, or equivalent. These converters have rated output current over 1000 mA. The A2071E circuit consumes roughly 300 mA. As we report below, we had problems with the ASD05-12S3 converter over-heating, failing altogether, consuming excess current, and generating noise. We switched to the slightly larger, but less costly, PYB10-Q24-S3 in March 2016.
Power to the driver sockets, and therefore to all LWDAQ devices, multiplexers, and repeaters connected to the driver, is controlled by three solid state switches and monitored by current sensing resistors. To turn off the device power, write a zero to the enable device power location. To turn the power on again, write a 0x01 to the same location.
In addition to power switching, the A2071 allows you to measure LWDAQ current consumption and power supply voltages. Driver socket zero on the A2071 is a virtual, on-board socket that gives access to ten monitor voltages. To select these voltages, we use device addresses zero through nine. Together, these voltages allow us to calculate the current delivered through the eight driver sockets combined, and the voltage at which it was delivered on the ±15V and +5V power supply lines.
Each monitor voltage differential, so it consists of a differential and common-mode component. The voltage is delivered to the power supply monitor's amplifier. To obtain accurate measurements of the power supply voltages and currents, we must calibrate this amplifier's common-mode and differential gain. We do this with a precision 5-V reference voltage, whose output is available in monitor voltages zero and one. Typical values are −0.020 V/V for common-mode gain and 64 V/V for differential gain.
|DAR||V diff (V)||V com (V)||Description|
|0||5β||0||differential gain reference|
|1||0||+5||common-mode gain reference|
|2||αI1||V1||+15 V current measurement|
|3||βV1||0||-15 V voltage measurement|
|4||αI2/2||V2||+5 V current measurement|
|5||βV2||0||+5 V voltage measurement|
|6||αI3||V3||-15 V current measurement|
|7||-βV3||0||-15 V voltage measurement|
|8||0||0||grounded common mode input|
|9||0||0||floating common mode input|
We use the sixteen-bit ADC to measure the voltage presented by each channel. Our lwdaq_A2037_monitor routine, in electronics.pas, shows how to combine the monitor voltages to calculate the current and voltage of the power supplies, and applies to the A2071 as well as the A2037. The Diagnostic Instrument takes several hundred measurements of each monitor voltage, and so measures current consumption with 10-μA precision and supply voltage with 1-mV precision.
The power monitor circuit measure the voltage supplied to external devices, so if you turn off the power, you should see these voltages drop slowly to zero. The current measured by the power monitor circuit is the current passing to the external devices, plus the power delivered to the indicator LEDs on the front panel, each of which consumes roughly 6 mA.
The power supply monitors are the basis of the Analyzer Tool, which maintains a database of device current consumption signatures in response to various command words. By comparing the current consumption of actual devices to those of ideal devices, the Analyzer Tool can check for problems in a LWDAQ system, and has proved particularly useful in large systems.
There are eight test pins on the A2071 circuit board. They are connected to the lower eight LEDs on the front panel. They are marked TP1..TP8 on the silk screen. The top LED, which is yellow, indicates the state of TP1 and the bottom LED, which is red, indicates the state of TP8. When the test pin voltage is HI, the LED turns on. You can look at the test pin voltages with an oscilloscope by hooking the probe onto one of the pins, and grounding the probe to one of the two ground pins below the test pins.
|Test Point||Logic Signal (Asserted when LO)|
|1||Configuration Switch Pressed|
|5||Delay Timer Not Zero|
|6||Repeat Counter Not Zero|
|7||Transmitting Device Address|
|8||Transmitting Device Command|
We use the test pins to help us find problems with LWDAQ components. We can, for example, trigger an oscilloscope off the Pixel Counter Clock or Line Counter Clock and look at the signals on an image sensor head.
|Test Point||Logic Signal (Asserted when LO)|
|1||Board VME Select|
|2||Board VME Activity|
|5||Delay Timer Not Zero|
|6||Repeat Counter Not Zero|
|7||Transmitting Device Address|
|8||Transmitting Device Command|
The A2071A plugs into a VME backplane. The test pins and indicator lights are the same, but there is no configuration switch or ethernet. The top two orange lights are VME Board Select and VME Board Activity.
After you apply power to the A2071E, the RCM6700 embedded sixteen-bit microprocessor module boots up and starts its TCPIP communication stack. The A2071E is ready to communicate a few seconds after power-up or harware reset by the front panel reset button. When operating with its default configuration, the A2071E listens for a TCPIP connection on port 90 of IP address 10.0.0.37. It services only one connection at a time, but starting with software version 6, it will accept any number of connections and service them in turn. Earlier versions of the software will reject any second attempt to connect by a LWDAQ client. By means of the Configurator Tool in our LWDAQ Software, we change the port and IP address of our A2071E.
The A2071E accepts communication in the LWDAQ message protocol. Here are the message identifiers recognised by the A2071E TCPIP interface, as implemented in the program that runs in the RCM6700 module. The code that runs in the A2071E is compiled from the same source we use for the A2037E, A2064A, A2064F, and A2101A. You will find all versions of this source code in the A2037E source code directory here. The C program is called C2037Exx.c, where xx is the version number. The compiled binary files that we upload to the RCM6700 are here. They are named C2071Exx.bin.zip. The first time we boot up the RCM2200, we hold down the configuration switch on the back of the A2071E to format its EEPROM file system and write default values to the configuration file.
The LWDAQ Software uses Tcl to open a TCPIP socket to the A2071E and transmit messages. It uses Tcl to receive message back from the A2071E. The Tcl routines that implement the LWDAQ TCPIP Messaging Protocol are in a file called Driver.tcl, which is one of the scripts in our LWDAQ distribution. You will find our software here.
The byte_write execution time on the A2071E is 40 μs minimum and 95 μs on average, including the time it takes to transmit the instructions to the RCM6700 over TCPIP. The transfer rate from the A2071E's RAM to the RCM6700's RAM is 4.3 MByte/s. The overall data transfer rate from A2071E RAM to a data acquisition computer is roughly 1.4 MByte/s. The stream delete rate when clearing the driver memory is 5.5 MByte/s.
The A2071A is a VME slave. It responds to all address cycles in its 512 kByte address space. Following the assertion of the VME backplane data strobes, the A2071A takes 150 ns to assert DTACK. The assertion of DTACK on a read cycle means that data is ready on the backplane data lines. On a write cycle it means the data written to the board has been received, and the cycle is over. When the backplane !SYSRESET signal is asserted, the A2071A resets itself.
Note: All our schematics and Gerber files are distributed under the GNU General Public License.
[10-MAY-18] The A2071A built with the A207102A printed circuit board requires a wire link from !RESET to !SYSRST and the track from !SYSRST to P6 must be cut. This allows the !RESET signal to reset the ring oscillator and registers in the P2071A firmware. Boards modified in this way have hardware version zero, HV=0. The A2071A build with the A207102B printed circuit board require no modifications and have hardware version one, HV=1.
The A2071E built with the A207101A/B printed circuit board has hardware version number zero, HV=0. These boards do not provide protection against an out-of-range voltage being returned from a faulty device, so U17 is in danger of over-heating. Furthermore, they have trouble reading out a camera over a 120-m cable because their pull-up and pull-down resistors are 1 kΩ instead of 10 kΩ.
The A2071E made with the A207101C printed circuit board provides protection resistors R117 and R118. If its pull-up and pull-down resistors are 1 kΩ, it still cannot read a camera out over a 120-m cable. Its hardware version is one, HV=1.
The A2071E made with the A207101C/D printed circuit board, with 10-kΩ pull-up and pull down resistors has hardware version two, HV=2.
[17-JUN-13] The A2071E with an LM6172M in place of U17 is vulnerable to a device setting R+ or R− outside the range 0..+3.9 V. For example, if the device wires R+ to +15 V, U17 will find its output shorted to 3.3 V through diode array U31. The op-amp overheats, breaks, and starts to bring down the ±15 V power supply. In the A207101C layout, we add 1 kΩ resistors R117 and R118 between the outputs of U17 and the U31 diode clamps. This modification is difficult on the A207101B circuit board, and would itself compromise the reliability of the circuit. We decide to leave the A2071Es that exist now as they are. They will be hardware version 0.
[07-AUG-13] We repair two broken A2071Es. In one, some problem with one of the DG411DY analog switches was pulling R+ and R− down to −4 V when we selected an empty driver socket. When combined with our problem with taking R+/R− outside the range −0.6-4.1 V, U17 was over-heating and dying. We replaced DG411DYs and U17 and board works fine. The other had a damaged U20. Neither fault appears to have originated because of the lack of R117 and R118 on the V0 hardware.
[29-JAN-14] Two months ago we received 5 A2071Es with V1 hardware, which includes R117 and R118. We omit R12 so as to indicate to the firmware the hardware is version one.
[03-APR-15] We find that the A2071E with V1 hardware won't read out a camera over a 120-m cable, while the A2037E does so with no problem. We replace the 1 kΩ resistors R14 and R15 with 10 kΩ, to mimic the A2037E pull-up and pull-down resistors. Now the A2071E reads out over 120 m. We present these observations in more detail here. We change the value of resistors R14, R15, R17, R18, R20, R21, R23, R24, R26, R27, R29, R30, R32, R33, R35, and R36 to 10 kΩ. This is the V2 hardware. We set up V2 by loading R12 (sets bit zero to zero) and omitting R13 (sets bit one to one).
[29-MAR-16] We have Q0213 returned from Genova, Italy. They reported that it was over-heating and shutting down. We open the case and see L1 is discolored. We apply power and after ten minutes, L1 and U8 are too hot to keep a finger on, but 3.3 V power is still present. The driver is still functional. The RCM6700 is hot also. We remove it from the board. After five minutes, L1 and U8 have cooled down. We connect 24-V power from a bench-top supply. Driver Q0213 draws 350 mA with the RCM6700 plugged in, and 190 mA without the RCM6700. Driver Q0142 draws 210 mA and 120 mA respectively. Driver Q0244 draws 350 mA and 190 mA respectively, then the 3.3-V power supply fails completely and the circuit draws 120 mA. Driver Q0245 draws 210 mA at 24 V without opening the box. It appears that our ASD05-12S3 converters are faulty. We have already decided to replace the ASD05-12S with the PYB10-Q24-S3. We will add to quality control a measurement of the driver 24-V input current consumption in future. We replace the ASD05-12S3 on Q0213 and Q0244. They now draw 190 mA for one second after applying 24 V, and 220 mA afterwards, when the RCM6700 module comes out of reset.
[30-MAR-16] We note excessive ground noise on the metal enclosure of a device plugged into driver Q0245, which is still equipped with the ASD05-12S3 converter.
We switch to Q0244, which has the PYB10-Q24-S3 converter, and obtain the following noise. The 24-V power supply to the driver remains the same.
The spikes drop from around 60 mVpp to 30 mVpp, while the harmonic pattern drops from 50 mVpp to 20 mVpp. We replace the ASD05-12S2 on drivers Q0244, Q0245, Q0213, and Q0142.
[19-AUG-16] We study the reception of serial bytes by the driver from LWDAQ devices. The bytes are marked by a 50-ns LO start bit, the eight data bits, each 50 ns, most significant to least significant, then a return to HI for at least 100 ns before the next transmission. The driver uses two versions of the serial logic signal TXI. One is TXIS, which is clocked by CK, the 40-MHz clock, and the other is TXIF, which is clocked by FCK, the 80-MHz clock. The state machine that receives the bytes is itself clocked by CK, and leaves its rest state when it detects a LO on TXIS. The first rising edge of CK disovers the LO. The second moves the receiver into state 1. The third moves it to state 2. The fourth rising edge clocks the value of TXIF into a shift register as the first serial bit. The rising edge of FCK occurs roughly 2 ns before the rising edge of CK. The question arises: will this timing give reliable reception for all phases of CK, for small variations in clock frequency, for reasonable jitter in the clock?
The Serialization.tcl program is a Toolmaker script that simulates variation in clock phase with random jitter and any number of serial bits. We can vary the delay between the time at which we sample TXI and the time of the rising CK edge that clocks the sample into the shift register.
We find reception for eight bits is reliable with jitter ±0.5 ns, clock period 25.0 ns, and delay 0-25 ns. Our delay is 2 ns, which is on the edge of the reliable window. We would do better to sample TXI with the falling edge of CK, which would give us a delay of 12.5 ns, in the center of the window. With a 12.5 ns delay, we can tolerate clock jitter of ±2.5 ns, or period range 25±0.5 ns. Given the proven reliability of the existing firmware, however, we deem it unwise to attempt an improvement to the de-serializer.
[29-JUN-17] We have firmware P2071A01.abl for the A2071A running with VME read and write time 160 ns from DS to DTACK. The top orange indicator is Board Select, meaning the address on the VME backplane selects the A2071A. The second orange indicator is Activity, meaning VME reads and writes are taking place.