TCPIP-VME Interface (A2087) Manual

©2019, Kevan Hashemi,alignment.hep.brandeis.edu

Contents

Description
Design
Operation
Test Pins
Development

Description

[30-SEP-19] The TCPIP-VME Interface (A2087) is a VMEbus Master with a TCPIP interface that allows us to communicate with VMEbus Slaves over a wired TCPIP connection. The A2087 acts as the LWDAQ Relay for on or more VMEbus resident LWDAQ Controllers, such as the LWDAQ Controller with VME Interface (A2071A).


Figure: TCPIP-VME Interface (A2087). The reset switch protrudes from the top left, above the idicator lamps. The configuration switch sits near the left edge of the circuit. The VME interface is provided by P1 on the top-right and P2 on the bottom-right. The TCPIP interface is provided by J2 on the bottom-left. The RCM6700 embedded computer is the module mounted on the board towards the bottom-left.

We communicate with the A2087 using the LWDAQ TCPIP Messages. The A2087 handles its TCPIP communication with an RCM6700 embedded microprocessor. The A2087 hardware is capable of providing the following VME functions. Our intention is to implement these functions in the P2087 firmware and C2087 software as we require them. The hardware version resistors, R22-R24, can be used to configure the board for various VME functions, such as master, slave, and arbitrator.

The A2087A is designed to replace the TCPIP-VME Interface (A2064). The A2087A acts as a LWDAQ relay, providing communication with one or more VME-resident LWDAQ controllers, such as the A2071A or A2037A, through its TCPIP interface. The A2087A is equipped with firmware P2087A and software C2087A. The A2087 always acts as a VME master. It implements only 24-bit addressing (A24 in VME terminology) with non-privelidged access (address modifier 0x39), and it implements only single-byte reads and writes. It does not handle interrupts in any way. It does not permits bus arbitration, but acts as the sole master for the VME backplane. It implements the LWDAQ base address in a manner backward-compatible with earlier LWDAQ relays, such as the A2064A. As a consequence of its backward-compatible base address implementation, the A2087A is incapable of writing to any VME address with least significant byte in the range 42-45.

Design

Note: All our schematics and Gerber files are distributed under the GNU General Public License.

S2087_1: RCM6700 Logic.
S2087_2: VME Data.
S2087_3: VME Address.
S2087_4: VME Controller.
S2087_5: Power Supplies.
A208701A: Printed circuit board version A.
Code: Firmware and software source files and object files.

Operation

[01-OCT-19] The A2087 provides a TCPIP interface with a VME backplane. It mates with VME connectors J1 and J2, which are present in the original VME specification, but does not provide connection to the extended specification connectors added in later years. Both J1 and J2 are 96-way DIN sockets. On the A2087 are two right-angle 96-Way DIN plugs. The top one is P1, which mates with J1. The bottom one is P2, which mates with J2.


Figure: VME P1/J1 Connections, Table 53 in VME Specification.

The TCPIP interface is provided by an RCM6700 embedded computer. The TCPIP interace presents a static IP address, by default 10.0.0.37. We can program with the Configurator Tool to use any IP address we like.


Figure: VME P2/J2 Connections, Table 54 in VME Specification.

We can restore the IP address of the RCM6700 to 10.0.0.37 by pressing the reset and configuration switches at the same time, then releasing the reset switch to allow the RCM6700 to boot up and notice that we are pressing the configuration button, at which point it will re-write its configuration to the default values, which includes setting the IP address to 10.0.0.37.

The A2087A is a TCPIP-VME Interface for use in VME-based LWDAQ systems. It replaces the A2064. The A2087A provides the following LWDAQ Controller address map, which is accessible to the LWDAQ Software through byte_writea, byte_read, and stream_read instructions. The LWDAQ Controller addresses appear on the VME Backplane. They are the same as twenty-four the bit VME addresses.

Address (Hex) Address (Decimal) Contents Read-
Write
000000000Harware Identification Number (87)R
0000001218Hardware Version Number (0-7)R
0000001319Firmware Version Number (1+)R
xxxxxx2A42VME Address Register 3 (A24-A31)W
xxxxxx2B43VME Address Register 2 (A16-A23)W
xxxxxx2C44VME Address Register 1 (A8-A15)W
xxxxxx2D45VME Address Register 0 (A1-A7)W
0000003F63RAM portalR
Table: LWDAQ Controller Address Map of the A2087A. An "x" in an address means "don't care". The LWDAQ controller address consists of the LWDAQ base address plus a one-byte

The LWDAQ Software's byte_write instruction carries only the lowest eight bits of the LWDAQ controller address. The upper twenty-four bits are stored in the address registers 1-3, having been written by earlier byte_write instructions to addresses 42-44. The A2087A intercepts byte_write instructions to any of the addresses 42-45, and uses these instructions to set its internal VME address registers instead of executing a VME backplane write cycle. This behavior is backward compatible to that of earlier LWDAQ relays, such as the A2064, but not identical. The A2064 would write to VME address locations while setting its own base address registers, so that the upper three bytes of the VME address would change during the write cycle. The A2064 was incompatible with any VME slave that implemented addresses with least significant byte 42-45, because such slaves could be written to at any time while the base address was being altered. The A2087 is incapable of writing to these same addresses, so it is incompatible with any slave that requires such addresses to be written. But the A2087A will not cause any unintended activity on such slaves during writes to its base address registers. If we want to use the A2087 with generic VME slaves, we must set the base address with a newer set_base_address instruction instead of a sequence of byte_write instructions.

The top address byte is driven onto the VME backplane for A24-A31, but the A2087A implements only twenty-four bit addressing on the VME backplane, so only the A8-A15 and A16-A23 base address bytes play a part in selecting a LWDAQ controller card. These cards will be configures with base addresses of the form 00xxxx00. If they have a !LADDR switch (long addressing), it must unasserted to select A24 addressing instead of A32. When the top three bytes of the base address are zero, the A2087A provides a hardware ID, hardware version, and firmware version in response do byte_read instructions. A stream_read from the RAM portal will produce an incrementing value 0-255, which will provide a gray-scale image for test software.

Internal to the A2087A is the VME Controller Address Map, which is the means by which the RCM6700 implements VME access cycles. The VME Controller Address Map appears in the external input-output address space of the RCM6700, and so may be accessed directly by the micrprocessor.

Address (Hex) Address (Decimal) Contents Read-
Write
2840Configuration Switch (0 or 1)R
2A42VME Address Byte 3 (A24-A31)W
2B43VME Address Byte 2 (A16-A23)W
2C44VME Address Byte 1 (A8-A15)W
2D45VME Address Byte 0 (A1-A7)W
2E46VME Address Control Register: AM5-AM0, !WRITE, !LWORDW
2F47VME Control Register, DS0, DS1, ASW
2F47VME Status Register, DTACK, BERRR
3048VME Data Byte 3 (D24-D31)RW
3149VME Data Byte 2 (D16-D23)RW
3250VME Data Byte 1 (D8-D15)RW
3351VME Data Byte 0 (D0-D7)RW
Table: VME Controller Address Map of the A2087A. These addresses are mapped into the RCM6700's external input-ouput address space.

When the RCM6700 in the A2087A executes a byte_write to write to a VME location, it does not set the A8-A31 address registers, but assumes these have already been written by byte_write instructions to the address bytes. Instead, the RCM6700 writes the eight-bit address provided by byte_write to VME Address Byte 0. If the address is even (A0 = 0), the RCM6700 writes the byte_write data to VME Data Byte 1, otherwise it writes to VME Data Byte 0. The RCM6700 writes 0xA7 to AM0-AM5, !WRITE, and !LWORD in the VME Address Control Register at location 46, specifying an A24, non-privelidged write cycle for two or fewer bytes of data. The relay writes the correct values of DS0, DS1, and AS to the VME Control Register at location 47. On a single-byte access at an even location, the relay asserts DS1 and AS by writing 0x06. On a single-byte access at an odd location, the relay asserts DS0 and AS by writing 0x05. The slave will now respond, and when the slave is done, it will assert DTACK. The relay reads location 47. When the value it receives is non-zero, either BERR or DTACK has been asserted. A write access either succeeded or failed, but it is in any case complete.

The execution of a LWDAQ byte_read instruction is similar. Instead of writing 0xA7 to the VME Control Register, the RCM6700 writes 0xE7 to unassert !WRITE. Instead of writing data bytes to the data registers before the start of the cycle, the RCM6700 reads the data bytes out of the same registers at the end of the cycle.

The same VME Controller registers can be used to implement two-byte and four-byte VME access cycles. In a single-byte write to an even address (A0 = 0), the relay writes to data byte 1 at location 50. In a single-byte write to an odd address (A0 = 1), the relay writes to data byte 0 at location 51. In a two-byte write to an even address (A0 = 0), the relay writes the most significant byte to byte 1 at location 50 and the least significant byte to byte 0 at location 51. In a four-byte write to an even address (A0 = 0), the relay has asserted LWORD by writing a 0 to !LWORD in the Address Control Register. Now it writes the four data bytes to VME Controller locations 48-51 in little-endian order: most significant byte first. On a two-byte access at an even location, the relay asserts DS0, DS1, and AS by writing 0x07 to the VME Control Register.

Test Pins

Test pins TP1 to TP8 are available on a SIP-12 connector behind the test lamps. The test pins are connected to the four amber and four red LEDs. When the lamp turns on, the test pin signal is Hi. The test pin definitions are given below, by this ABEL code exerpt. We have OR as #, NOT as !, XOR as $.

TP1  = CSW $ LNK;
TP2  = BAZ;
TP3  = DEN0 # DEN1 # DEN2 # DEN3;
TP4  = !DCK0 # !DCK1 # !DCK2 # !DCK3;
TP5  = DDIR;
TP6  = !ACK0 # !ACK1 # !ACK2 # !ACK3 # !ACK4;
TP7  = DTACK # BERR;
TP8  = CDS;

With these definitions, the front panel lights show clearly when data is passing into the VME backplane, and when it is coming out. The combined Configuration Switch and Link indicator flashes when we have ethernet activity and when we press the configuration switch.

Development

[01-APR-19] Schematic complete.

[22-JUL-19] Printed circuit board A208701A arrived.

[26-SEP-19] Firmware version three (FV3), defined by P2087A03, combined with software version two (SV2), defined by C2087A02, provides the first fully-functional TCPIP-VME Interface for use with VME-resident LWDAQ systems. We can replace one of our A2064A interfaces with the A2087A and read out a camera attached to the VME crate with no change in the LWDAQ data acquisition settings. We check the stream write and stream delete functions of the RCM6700 software using a Toolmaker script and our Driver Checker program.

[16-OCT-19] Firmware version four (FV4) provides better test pins. We have two new and fully-functional A2087A circuits tested.